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Evaluating and Improving Emulator Performance
With functional verification becoming the largest task in the development of an ASIC
or large FPGA, many engineers are looking at simulation acceleration or emulation as a way to speed development. Engineers today can choose from a number of different platforms.
Retargetable Transaction-Based System Level Verification
Functional verification has become the dominant resource issue in developing SoCs. The increasing gate capacity of integrated circuits and the corresponding ability to place an entire system, complete with one or more software-controlled processors, on a single chip has put increasing pressure on conventional simulation as the sole means of validating complete chip functionality.
Methodology and Code Reuse in the Verification of SOCs — Zaiq Technologies
Rapid developments in semiconductor technologies have opened a broad spectrum of opportunities for the electronics industry to produce complex systems from a number of pre-designed cores on a single chip. System-on-Chip (SoC) designs bring new verification challenges that become critical issues under the 'time-to-market' pressure. The reuse of verification code and methodology is a major factor providing significant reduction of the overall verification costs. A high-level description of the C-based verification system used for the verification and co-simulation of SoCs is described. In addition to this C language abstraction level, a set of pre-designed low-level C and VHDL routines create a powerful verification framework. The proposed verification methodology has proven to be reusable across a number of technologies and applications. The verification system's reusability is achieved by using a flexible user interface, environment structure, testbench design and verification methodology.
Verification of Skew and Jitter Tolerance and Compensation in High-Speed Interfaces — presented by Zaiq at DVCon
Historically, design engineers implementing high-speed interfaces have met numerous challenges in maintaining interface signal timing relationships and signal quality. Issues such as skew, jitter, crosstalk, and noise have been addressed through a combination of analog circuitry and board/chip physical design rules. Analog circuitry has been used for signal conditioning, filtering, impedance matching, and noise suppression, while physical design rules have targeted skew and crosstalk minimization.
In this paper we propose a common verification approach applicable to a variety of high-speed interfaces and based on reusable verification components that insert and monitor skew and jitter.
A Loosely Coupled C/Verilog Environment for System Level Verification
In this paper, we present a software C-Verilog interface, which is designed for the functional verification of any type of large system design. As a company specializing in ASIC verification, working with a wide range of systems including routers, parallel processors, and video applications, we not only developed this tool, but we are actively using it in large development environments with a variety of systems. In this paper, we will discuss some of the major concepts in this type of environment, along with the issues, and our experience with this tool in actual large development environments.
The Rise of Third Party Design and Verification Services
In today's economy, a company's very survival often depends on its ability to bring fully functioning products to market on time. This is especially true in the electronics industry, where a product's practical market window can now be measured in months instead of years! This truncated timeframe, coupled with the ongoing chronic shortage of qualified electrical engineers, make it difficult for electronic design and production companies to remain competitive.
To combat this problem, many engineering organizations have begun to use third-party vendors, such as ASIC Alliance, who specialize in the design and verification of electronic systems. With its Time-to-Revenue Design Engineering SolutionsSM, ASIC Alliance complements and extends the internal design groups of engineering organizations and helps them solve their most challenging design and verification problems within critical time-to-market deadlines.
Debugging Embedded Systems — ARM, Inc.
A significant portion of product design time is spent on integration and debugging of both hardware and software. This is especially true for systems with real time constraints such as engine management, hard disk control and modems. Deeply embedded cores (i.e. microprocessors which are buried within the heart of an ASIC or custom chip) have made the debug of such systems progressively more difficult as there is often limited access to the processors' busses and signals. This is worsened by the use of multi-processor systems such as the controller-DSP architectures common to hard disk drives, pagers and cell phones. An approach to addressing these issues is presented.
Developing Pre-Silicon Prototypes of Embedded System-on-Chip Designs — Aptix, Inc.
Engineers developing complex embedded System-on-Chip (SoC) designs are increasingly finding that traditional verification techniques are inadequate for delivering bug- free first-pass silicon. Hardware design problems made evident by complicated interactions among proprietary hardware, integrated third-party IP, low- level firmware, communication protocols, operating systems, and application software simply are not discovered by traditional simulator/testbench approaches. Companies that wait until test silicon is available before developing and integrating application software often find their market window closed when the product arrives. Many companies are turning to pre-silicon prototypes built from multiple FPGA devices as a technique for meeting these challenges. An approach to address these issues is presented.
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