Retargetable Transaction-Based System Level Verification

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Abstract
Functional verification has become the dominant resource issue in developing SoCs. The increasing gate capacity of integrated circuits and the corresponding ability to place an entire system, complete with one or more software-controlled processors, on a single chip has put increasing pressure on conventional simulation as the sole means of validating complete chip functionality. Most SoCs are multi-lingual, that is, they support multiple standard internal and external interface standards, implemented with third-party IP. Assuring that the custom and reused IP is correctly integrated and can be programmed to perform the intended functions while conforming to industry interface standards is a daunting verification challenge. For long-running linear processes, for example booting an operating system, simulation has simply run out of gas.

Transaction-based verification improves performance dramatically by allowing large amounts of data representing single or multiple clock cycles to be passed into simulation without multiple calls. Until now, verification environments have been event based, which means they have to provide data every clock cycle or even every sub-cycle. Transactions, on the other hand, deal with architecturally visible data types. For example, an Ethernet transaction deals with an entire Ethernet packet; a PCI DMA bus transaction deals with an entire burst transfer.

Synthesizing the design-under-test and all the cycle-accurate portions of the test bench, and exercising the resulting netlist in a hardware emulation environment (instead of on a general-purpose workstation), results in performance improvements over simulation by three to four orders of magnitude. Dramatic productivity gains for the test developers are also obtained with the described methodology.


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