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Opportunities

Northeastern Region Openings
Northeast Account Executive
Verification Engineer
FPGA Design Engineer
Technical Recruiter

Western Region Openings
SystemC Behavioral Model Developer
Verification Engineer
FPGA Design Engineer
Technical Recruiter

Northeastern Region Openings Northeast Account Executive Job Responsibilities: As an Account Executive you will be responsible for developing, maintaining and growing client relationships. You will hold primary responsibility for direct sales to all potential clients in your assigned territory/accounts along with identifying and opening new accounts. Responsible for day to day management of the assigned territory Initiate sales activities to stimulate, encourage, establish and develop account relationships Identify, evaluate and respond to key business issues of your account and develop, present and demonstrate our products and services to potential customers. Develop, deliver and present professional technology proposals. Set and manage appropriate business expectations with customers Interact with our engineering professionals to ensure clients receive timely delivery of high quality products and services. Job Requirements: 5+ years experience of successful direct sales experience in Design Services (required) 3+ years experience of successful direct sales experience in EDA tools or IP (preferred) BSEE + MBA or equivalent Large rolodex in the territory of executives and senior level design managers A solid understanding of ASIC and FPGA design and verification procedures and processes Demonstrable track record opening new accounts and expand existing accounts Recent closure record of design services engagements in key accounts Experience selling large, complex services engagements Excellent written and verbal communication skills submit your resume Verification Engineer Job Responsibilities Zaiq Technologies is a recognized leader in verification of complex ASICs, FPGAs, and systems. You will use C++, SystemC, Vera or other object-oriented verification languages to verify our customer's designs. You will work as a full time employee of Zaiq, either individually or as part of a Zaiq team. Tasks include: Determine verification methodology and environment Write the verification test plan Specify, develop, or enhance the verification environment and transactors using C/C++ and SystemC. May develop tests in Vera, Specman e, or other languages/. May develop high level un-timed model transaction model May develop bus functional models in Verilog or VHDL Develop regressable, self-checking test suites to implement the test plan. Isolate design failures and assist in bug resolution. Requirements 10 years overall experience in logical verification Have successfully defined, developed, and used multiple verification environments, using a variety of methodologies and techniques Experienced team leader, able to set technical direction and guide junior team members Experience with C/C++ and SystemC is required. Experience with Vera, Specman e or SystemVerilog is a plus. Experience with coverage monitors and constraint based randomization is a plus Experience with assertions is a plus. Experience with media processing and consumer electronics is a plus. Based in Zaiq's Woburn, MA design center Ability to travel is a plus submit your resume FPGA Design Engineer Job Description You will develop RTL code to implement FPGA-based digital designs, working from specification through to system integration. Projects will range from small through multi-million gates. Most projects implement a combination of control logic (bus interfaces and state machines), Digital Signal Processing, and Embedded Processors. You will work as a full time employee of Zaiq, either individually or as part of a Zaiq team, consulting to Zaiq’s clients. Responsibilities include: Write functional specifications Functional partitioning, block diagram, and detailed design spec RTL coding of design in Verilog or VHDL Develop testbench and verify at the block level Synthesis, mapping to target device, and timing closure May include modeling with Matlab or C++ May include lab debug or HW/SW integration Requirements 5+ years experience, including successful completion of multiple FPGA implementations Experience targeting Xilinx and/or Altera FPGAs is required. Familiarity with Synplicity, Xilinx ISE, and Altera Quartus tools Coding experience in Verilog and VHDL is required. Implementation of designs with multiple clock domains is required Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed Experience implementing DSP algorithms in RTL is preferred Experience interfacing with ARM or PowerPC etc is preferred Based in Zaiq's Woburn, MA design center. submit your resume Technical Recruiter Job Description As a technical recruiter you will help grow Zaiq’s team of experienced engineers, working with engineering and HR. Locate candidates matching Zaiq’s descriptions through Zaiq sources and your own network. Screen candidates and update Zaiq contact database. Manage candidates through interview and hire activities. This is a part-time hourly contract position with flexible hours and location. Requirements Demonstrated success in recruiting R&D engineers with the following skills: FPGA and ASIC design, logical design verification, behavioral modeling using C/C++. Energetic and engaging phone personality with professional attitude. Good organizational skills Flexible, able to adapt to Zaiq process and requirements submit your resume Western Region Openings SystemC Behavioral Model Developer Responsibilities: Develop Behavioral Models of IP cores, design blocks and subsystems. Use C++ and SystemC to model the target behavior at the Transaction Level. Assemble the behavioral models into system configurations and use them to predict and verify performance, latency, bandwidth, and throughput of the target architecture. You will be based in our CA design center to: Write the implementation spec for the behavioral model Develop transaction level behavioral models in C++ and/or SystemC Develop a test suite or exerciser to run against the models Support design architects in analyzing results and exploring design architectures Integrate the behavioral model with the logical verification environment to establish congruence of architecture and implementation Requirements 5+ years experience in logical verification and/or modeling Experience modeling hardware at the transaction level, clock cycle level, and register transfer level Experience in using SystemC and C++ is required. Experience with Vera, Specman e or SystemVerilog is a plus Firm understanding of object oriented programming concepts and techniques Experience developing models or other applications using multiple processes and threads, on both Solaris and Linux Excellent software engineering skills, including programming style, configuration and release management, and documentation Have successfully defined, developed, and used multiple verification environments, using a variety of methodologies and techniques Experience with industry standard busses and embedded processors or DSP is a plus Based in Zaiq's San Jose, CA design center Ability to travel is a plus submit your resume Verification Engineer Job Responsibilities Zaiq Technologies is a recognized leader in verification of complex ASICs, FPGAs, and systems. You will use C++, SystemC, Vera or other object-oriented verification languages to verify our customer's designs. You will work as a full time employee of Zaiq, either individually or as part of a Zaiq team. Tasks include: Determine verification methodology and define the environment Write the verification test plan Specify, develop, or enhance the verification environment and transactors using C/C++ and SystemC May develop tests in Vera, Specman e, or other languages. May develop high level un-timed transaction model May develop bus functional models in Verilog or VHDL Develop regressable, self-checking test suites to implement the test plan Isolate design failures and assist in bug resolution. Requirements 10 years overall experience in logical verification Have successfully defined, developed, and used verification environments, using a variety of methodologies and techniques Experienced team leader, able to set technical direction and guide junior team members Experience with C and object oriented programming in C++ is required Experience with SystemC, Vera, Specman e or SystemVerilog is a plus Experience with coverage monitors and constraint based randomization is a plus Experience with media processing and consumer electronics is a plus Based in Zaiq's Woburn, MA design center Ability to travel occasionally is a plus submit your resume FPGA Design Engineer Job Description You will develop RTL code to implement FPGA-based digital designs, working from specification through to system integration. Projects will range from small through multi-million gates. Most projects implement a combination of control logic (bus interfaces and state machines), Digital Signal Processing, and Embedded Processors. You will work as a full time employee of Zaiq, either individually or as part of a Zaiq team, consulting to Zaiq’s clients. Responsibilities include: Write functional specifications Functional partitioning, block diagram, and detailed design spec RTL coding of design in Verilog or VHDL Develop testbench and verify at the block level Synthesis, mapping to target device, and timing closure May include modeling with Matlab or C++ May include lab debug or HW/SW integration Requirements 5+ years experience, including successful completion of multiple FPGA implementations Experience targeting Xilinx and/or Altera FPGAs is required. Familiarity with Synplicity, Xilinx ISE, and Altera Quartus tools Coding experience in Verilog and VHDL is required. Implementation of designs with multiple clock domains is required Thorough understanding of appropriate coding styles for FPGAs, and trade-offs for density and speed Experience implementing DSP algorithms in RTL is preferred Experience interfacing with ARM or PowerPC etc is preferred Based in Zaiq's Woburn, MA design center. submit your resume Technical Recruiter Job Description As a technical recruiter you will help grow Zaiq’s team of experienced engineers, working with engineering and HR. Locate candidates matching Zaiq’s descriptions through Zaiq sources and your own network. Screen candidates and update Zaiq contact database. Manage candidates through interview and hire activities. This is a part-time hourly contract position with flexible hours and location. Requirements Demonstrated success in recruiting R&D engineers with the following skills: FPGA and ASIC design, logical design verification, behavioral modeling using C/C++. Energetic and engaging phone personality with professional attitude. Good organizational skills Flexible, able to adapt to Zaiq process and requirements submit your resume

Notice to Recruiters and Agencies
Zaiq Technologies prefers to recruit candidates directly rather than through a third party. Do not submit or present your candidates via email, fax, phone, mail, verbal referral or any other means to Zaiq or any employee of Zaiq Technologies. Zaiq will only pay a fee for candidates submitted or presented after there is a signed recruiting agreement in place between Zaiq and the recruiter or agency, and the candidate is submitted for a specific requisition. In the case of candidate(s) submitted or presented to Zaiq by a recruiter or agency without a signed agreement in place or without a specific open requisition, Zaiq Technologies explicitly reserves the right to pursue and hire those candidate(s) without any financial obligation to the recruiter or agency.

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