Common Reuse Platform Required
--EXECUTIVE VIEWPOINT--
Andreas Meyer is chief technology officer at ASIC Alliance in Woburn, Mass. He is also the chief architect of a new SystemWare tool for verification IP reuse coming soon from ASIC Alliance.
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Woburn, Mass. - January 15, 2001 (Electronic News 1/15/01) Industry attention has been focused on the front-end challenges of intellectual property (IP) evaluation and licensing, but no one is adequately addressing the real implementation issues involved in actual IP reuse. For IP reuse to deliver on its promise there must be a common platform for hardware, software and verification reuse. In addition, successful IP reuse will require a methodology and tools for the encapsulation and visualization of IP to permit an architectural approach to IP integration.
Many of the current cores that are available fall into two areas: standard interfaces and general-purpose devices. These areas do rather well with the current state of IP integration. The application program interface (API) of general-purpose processors is well understood and the standard interfaces have public specifications. When design issues surface, it is generally possible to determine if the fault lies in the core or in the system. As a result, reasonable levels of reuse can be achieved for these types of cores with current methodology.
For more specialized complex cores, however, integration and debug become more difficult for several reasons, including the necessity to create a verification suite to test a core in a system environment, the need to see inside the core register transfer level (RTL) to determine the source of errors, and the ability to program complex cores appropriately.
Current IP core verification suites tend to be very inward-focused. They are used to determine if the core is working correctly as instantiated. The more important question, which is not addressed, is whether the system is working correctly with the core? Since most errors occur in the integration, it means that a system-level verification environment must be recreated for each core instantiation. This is a time-consuming task that requires detailed knowledge of the core. Unfortunately, in the case of complex special-purpose cores, it is required. In our experience, even cores that have been used successfully in previous projects still have a significant number of functional bugs. Simply by being integrated into a new environment with a different stimulus, cores reveal new bugs.
Since verification test writing is such an enormous task, it is critical to achieve a high level of reuse in this area. This reuse requires a significant shift in the approach taken to create verification tests. Large blocks of IP cannot be viewed as blocks of RTL code that must be exercised. Rather, a system-level approach must be used that leverages the encapsulation and software techniques and focuses on providing domain-specific testing.
The first job of IP verification code is to determine if the block of IP is working as expected after it is integrated into the new environment. This is a critical task and the IP verification must be able to determine that the block is working correctly as a stand-alone device.
While the operation of a stand-alone block must be verified, the goal of domain-based verification is to determine whether disparate IP blocks interoperate correctly. New project-specific functionality must also be integrated into the verification environment. Furthermore, this environment must be verified with real traffic flowing through the devices and real software applications interacting with the devices.
The key advantage of higher-level operations is that they will be useable not only for testing a particular block, but also for testing operations rather than driving specific signals. If a block of IP is designed to handle a specific protocol, for example, asynchronous transfer mode (ATM) cells, then the verification environment must be able to generate valid ATM cells and the tests must create ATM cells, drive them through the system, and determine if the block works at an algorithmic level. This type of an environment can be leveraged from a block-focused test to a system-level testing environment.
Another key requirement for effective reuse is a standard API, which is used for all software activity from verification to application development. Standardized software interfaces are becoming more common for IP, but are still critical for special-purpose designs. Integrating a design is far simpler if there are drivers to perform all the common operations, if the RTOS integration has already been performed, and if all of this is available to the verification and software teams at the start of the project.
The effectiveness of IP will be dramatically reduced if there is ever a need to understand the core below a block level. Encapsulating the core so that the users of the core need never see the low-level code is critical to leveraging the advantages of IP.
Encapsulation is complex simply because it must be exhaustive. If any section is left out, then engineers will be forced to dig into the details of the IP to figure out how to use it. For encapsulation to work, all bus interfaces must be fully defined, the block diagram of the IP block must be clearly specified, visualization tools must be provided so that engineers can see what is currently happening within those blocks, and a software API must be provided to ensure that the IP is correctly controlled and verification code is able to properly exercise and query the IP. Finally, log files must be available to determine the correct operation and performance of the IP. All of these components together comprise a vertical slice—one complete section of what will make up a new system-on-a-chip (SOC) design.
This single slice can be developed and tested, and the software drivers can be integrated in a stand-alone fashion. Once the slice is integrated with other slices, some level of consistency between the layers is helpful to ease the software integration issues.
Each vertical slice is an independent, encapsulated block of IP. For this approach to be successful, it is critical that the interfaces are carefully designed and consistent with the overall methodology and that they provide sufficient tools for designers to be able to understand the internal state and functionality without delving into the internals.
By using a complete vertical slice built around a complex special-purpose core, we have been able to achieve 50 to 80 percent reuse of design and verification code on projects containing multiple complex cores that required modification between projects. This method of encapsulation enables engineers to successfully work with complex cores of greater than 1 million gates without a detailed understanding of the underlying RTL code. Evaluation and licensing are important issues to resolve if IP reuse is to be successful. But the real key to actually reusing IP lies in solving the system-level verification challenge.
Andreas Meyer is chief technology officer at ASIC Alliance in Woburn, Mass. He is also the chief architect of a new SystemWare tool for verification IP reuse coming soon from ASIC Alliance.
About Zaiq Technologies, Inc
Headquartered in Woburn, Mass., Zaiq Technologies, Inc. is a leading provider of total design engineering solutions for companies that develop complex telecommunications, networking and computer products. The Company's innovative domain-specific design methodologies enable the creation and integration of reusable IP. As a result, customers are able to achieve breakthroughs in the time-to-market and time-to-revenue delivery of complex systems. Information about Zaiq and its services are available by phone at 781-932-2442, by e-mail at
info@zaiqtech.com or on the Internet at
http://www.zaiqtech.com.
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