ZAIQ TECHNOLOGIES ANNOUNCES PREP™ 4.0 - A SEAMLESSLY RETARGETABLE SYSTEM VERIFICATION ENVIRONMENT
Latest version productizes the SYSTEMware™ Family's inherent transaction-based support of simulation, hardware acceleration and emulation
Woburn, Mass. - September 16th, 2003 - Zaiq Technologies, Inc., a leading provider of complete design engineering solutions, today announced the release of the forth version of its Pre-configured Reusable Environment and testing Platform (PREP™). PREP provides chip and system designers with a pre-configured verification environment for complex designs, along with a methodology to comprehensively and efficiently test those designs. PREP 4.0 improves upon Zaiq's previous versions of the PREP environment by supporting the recently announced Accelera standard - Standard Co-Emulation Application Programming Interface (SCE-API) - enabling designers to quickly and easily retarget their verification environment from simulation to acceleration or emulation.
"As design complexities change from project to project, customers need the flexibility to target their verification environment to the most effective verification approach, " said Bernard Gilbert, Zaiq's President and CEO. "SYSTEMware, and our new release of PREP, allows customers to simultaneously support the most common verification products like simulators, accelerators, FPGA prototype boards and emulators from the same transaction based environment. Zaiq has over the past several years developed a number of interfaces to hardware-assisted products, however, the advent of the Accelera SCE-API interface has allowed us to productize on an industry standard."
"The SCE-API offers an intelligent interface for many types of tools," noted Brian Bailey, Accellera Interfaces Committee Chair. "Since verification requirements are increasing, in many cases, a single tool isn't enough. In these cases, a standard interface between the tools can bring the best in class tools together, and allow for better re-use of models among different design tools. We are happy to see industry support of the SCE-API standard."
As part of Zaiq Technologies SYSTEMware family, PREP allows rapid deployment of DV environments for projects with an initial pre-configured environment. PREP supports unit, chip and system-level testing, including constrained randomized testing, which results in increased test coverage and greater product viability. Developed in C and C++, PREP supports Verilog, VHDL and C/C++ standard usage and tools, and interfaces with languages like SystemC, System Verilog, Vera and e. PREP's standard verification environment facilitates verification IP reuse and provides powerful, reusable support libraries.
About Zaiq Technologies, Inc
Zaiq Technologies, Inc. enables its customers to meet critical product development objectives by offering a complete line of specialized design and verification products and services. Zaiq is a recognized leader in system level design and verification for complex, high-performance, system-on-chip (SoC & SoPC), ASIC and FPGA based systems. Selected for two consecutive years on the Inc 500 list of fastest growing companies, Zaiq Technologies was founded in 1996 and has completed over 400 assignments.
For more information call toll free 877-351-8299, by e-mail at info@zaiqtech.com, or www.zaiqtech.com.
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