HDL Realization

Zaiq provides complete development services for Verilog, VHDL, and C-based High Level Design Languages. At Zaiq we understand that HDL realization is not a simple coding task, but rather impacts the efficiency and overall correctness of the entire project. HDL coding styles can greatly influence the success or failure of synthesis and timing efforts, system verification, design for test, and physical design. The most efficient HDL realization can occur only with complete front-to-back design service experience. Zaiq has that experience. At Zaiq we use advanced linting and code development styles to optimize HDL Realization.

Zaiq has developed a collection of coding rules and guidelines to help ensure that the HDL generated by Zaiq for its customers is readable, modifiable, and reusable. A comprehensive set of guidelines helps to achieve optimal results in synthesis & verification and simulation as well. The basic underlying goal of these guidelines is to develop HDL code that is simple and regular. Simple and regular structures are inherently easier to design, code, verify, and synthesize than are more complex designs. The overall goal for any reusable design should be to keep it as simple as possible while meeting its functional and performance goals.

Zaiq adheres to the following coding principles:

Basic Coding Practices
Guidelines that address basic coding practices, focusing on lexical conventions and basic HDL constructs (i.e. naming conventions, header definitions, comments, file layout, port ordering, VHDL/Verilog specific restrictions, labeling, etc.).

Coding for Portability
Guidelines that address the creation of code that is technology independent, compatible with various simulation tools, and easily translated from VHDL to Verilog or vice a versa.

Clocks and Resets
Guidelines for creating simple clocking and reset structures. These guidelines will facilitate user understanding of the reusable blocks and will produce optimum synthesis results.

Coding for Synthesis
Guidelines that address the synthesis issues of testability, performance, simplification of static timing analysis, and gate level circuit behavior that matches that of the original HDL Code. These guidelines will ensure code creation that achieves the best compile times and synthesis results.

Partitioning for Synthesis
Guidelines that address design partitioning so as to achieve optimum synthesis results, faster compile runtimes, and the ability to use simpler synthesis strategies to meet timing.

Designing with Memories
Memories present special problems for reusable design, since memory design tends to be foundry specific. Reusable IP must be designed to deal with a variety of memory interfaces. Therefore guidelines for dealing with these issues, in particular, designing with synchronous and asynchronous memories are essential.

Code Coverage
Guidelines specifying the methodology for utilizing code coverage tools that measure path coverage as well as statement coverage for the purpose of analyzing how well a given test or test set exercises a design and for checking redundancies in the design itself.

Coding for Verification
Zaiq has developed guidelines for the coding of RTL to achieve an optimum flow through the various functional and logical verification processes


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