Synthesis and Timing Verification

With the advent of more complex systems and higher density implementation technologies, systems using advanced synthesis techniques and the verification of the associated timing has been slowly merging into one activity. Zaiq has been actively providing services in these areas and has implemented some the industries most complex systems and System-on-on-chip (SoC) ASICs. Some of the synthesis and timing services that Zaiq provides are:

Design for Timing Closure: Logic Design Issues

Timing and synthesis issues include interface design, synchronous or asynchronous design, clock and reset schemes, and selection of synthesis strategy. The proper design of block interfaces can make timing closure, both at the block level and system level, a local problem that can be (relatively) easily solved. Zaiq has developed guidelines for both synchronous design and asynchronous design, needed to maintain design quality and design effort repeatability, especially when asynchronous design styles are required. Clock and reset guidelines and strategies are critical due to the impacts they have on all phase of the design process. Zaiq understands that documented synthesis strategies and guidelines for complex system and SOC design are essential to close the timing loop.
Design for Timing Closure: Physical Design Issues

During the later stages of the logic design phase, timing closure becomes primarily a physical design issue. The questions becomes whether the design can be placed and routed to meet the timing constraints of the design. One of the keys to achieving rapid timing closure in physical design is to plan the physical design early, and to incorporate ever increasing accurate timing information based on physical design back into the design process. Zaiq supports floorplanning and timing extraction, synthesis strategy and time budgeting, utilizing hard IP, and clock distribution.
System Interconnect and On-Chip Buses

A major problem in reuse-based design is the large number of different bus architectures used in chip designs. This fact makes interchange of IP very problematic. To address this problem, some companies have attempted to standardize on a single bus. However, the requirements of different designs have prevented this approach from being successful. The VSIA has proposed a different approach. Under their proposal, IP blocks would be designed with VSI standard interfaces. A series of adapters would then bolt on the IP, allowing the IP to work with any on-chip bus. Other product companies have decided to standardize on a few buses, typically three or four, and to design IP to work with all of these standard buses. Usually this means that IP is designed so that the interface block is a separate subblock of the IP. Three or four different interface blocks are designed to allow the IP to interface to all the standard buses.

Zaiq has remained skilled at implementing and using the "most likely" group of bus/interconnect technologies being employed by the industry. This requires on going research/training of efforts such as those by the VSIA, and a vigilant watch of the industry standards and trends. The design of the on-chip busing scheme that will interconnect the various blocks in an system or SOC design is an integral part of the IP selection and design process and an area that Zaiq is adding value to our customers.
Design for Bring-Up and Debug

Due to the complexity of system and SOC designs, Zaiq is developing strategies and guidelines for the bring-up and debug of the design. The most effective debug strategies usually require specific features to be designed into the chip. Without effective debug structures, even the simplest of bugs can be very difficult to troubleshoot on a large system or SOC design. Zaiq has created modified verification environments that can easily be ported to a laboratory environment.
Design for Low Power

With portable devices becoming one of the fastest growing segments in the electronics market, low power design has become increasingly important. Traditionally, design teams have used full custom design to achieve low power, but this approach does not give the technology portability required for reuse-based design. Zaiq consultants are trained, and skilled in current and monitoring future strategies/guidelines for low power design.
Design for Test (DFT)

With the ever increasing complexity and density of SOC designs, the demands for high yields, and the cost of test (i.e. on the tester floor), DFT is taking a prominent role in the system and SOC design processes. Zaiq support services include strategies/guidelines for DFT (i.e. scan, BIST, JTAG, etc.).


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