System Verification

Zaiq Technologies is the industry leading service provider for system verification. Using its comprehensive SYLVER verification methodology, Zaiq has verified some of the industry's most complex ASIC and system designs.

Verifying functionality and timing at the system level is probably the most difficult and important aspect of design. It is estimated the verification effort can be from 50 to 80 percent of the overall design effort. For complex system solution, verification must be an integral part of the design process from the start, along with synthesis, system software, and lab debug strategies. Successful and rapid system level verification depends on the following key factors; quality of the verification plan, quality and abstraction level of the models and testbenches used, quality and performance of the verification tools, verification re-use and finally, the robustness of the individual pre-designed or reusable IP.

Zaiq has developed a verification strategy and guidelines for generating test plans that will allow for rapid closure of the verification effort. The strategy has at its foundation the following key components:

1. The verification of leaf nodes (i.e. lowest level blocks) of the design hierarchy are functionally correct as stand alone units.
2. The verification of the interfaces between blocks are functionally correct, first in terms of the transaction types and then in terms of data content.
3. Verification simulates a set of increasingly complex applications on the full system culminating in randomized tests.
4. Complete Software verification may require Prototyping the system and running a full set of application software for final verification.
5. Up front Criterion must be set for when it is appropriate to release the chip to production.

At Zaiq we consider the following areas as the key verification tasks.

• Interface Verification
  

  System level verification consists primarily of verifying the interfaces and interactions between the blocks. Interface testing begins by testing all transaction (i.e. permitted sequences of control and data signals) types that can occur at each interface. Once the transactions have been verified, it is necessary to verify that the subblocks behave correctly for all values of data and all sequences of data that it will receive in actual operation (i.e. or as close to completion as possible given cost and schedule constraints).

• Functional Verification
  

  Functional verification consists of exercising the entire design in simulation using a full functional model for most, if not all, of the blocks. The ultimate goal of this aspect of verification is to try to test the system through simulation as it will actually be used. This form of verification presents some major challenges. Conventional simulation simply is not fast enough to execute the millions of vectors required to run even the smallest fragments of application code. To address this issue, Zaiq has developed processes and techniques that will increase the level of abstraction of the system so that software simulators running on workstations run as fast as possible.

• Application-Based Verification
  

  Running significant amounts of real application code is the only way to reach an acceptable level of confidence in the verification of many system design efforts. For most designs, this level of testing requires running at or near real time speeds. Many times t he only available technologies for achieving this kind of performance involve some form of rapid prototyping. Zaiq has incorporated processes for implementing (i.e. all or several) of the available rapid prototyping techniques. At this time these options are: FPGA prototyping, emulation-based testing, and real silicon prototyping.

• Gate-Level Verification
  

  Zaiq supports gate level verification processes that incorporate the following technologies:

  1. Formal verification to verify correspondence between the HDL and final netlist.
  2. Static timing analysis to verify timing.
  3. Gate level simulation (i.e. unit delay or full timing) to compliment formal verification and static timing analysis.
  4. Scan, JTAG, BIST, and silicon vendor specific test structures for verification of manufacturability.


• Verification Re-use
  

  Zaiq has developed verification IP with modular verification blocks that plug and play into system level verification environments.

• Specialized Hardware for System Verification
  

  The limitations of software simulators running on workstations have long been recognized at Zaiq. Simulation has never provided enough verification bandwidth to do really robust system simulation. Currently the focus on solving this problem has been hardware accelerators, emulation and silicon prototyping platforms. These systems hold promise for addressing the problems of high-speed system verification, and therefore, Zaiq is developing strategies and processes that support all, several, or the most promising technology.

• Software Driven Verification
  

  As the software content in SOC designs increases, hardware/software co-development and software-driven verification becomes increasingly important. Software-driven verification plays two key roles in an SOC verification strategy:

  1. Verification of the hardware using real software.
  2. Verification of the software using real hardware (i.e. emulation model), well before the actual system is built.

  Zaiq's SYLVER verification methodology supports hardware/software co-development and software-driven verification. Additionally, SYLVER based verification environments can be used to emulate actual lab debug activities.

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