Verification Products

Verification IP | PREP™ | TestBenchPlus™

Verification IP
Verification Components (VCs) are reusable verification intellectual property that allow you to increase engineering productivity and efficiency via re-use. SVCs are building blocks used to verify industry-standard functionality. SVCs reduce your overall development costs by providing domain-specific knowledge transfer and shortening the time it takes to verify your system.

See available VCs below.

Verification Components (VCs)

Communications SVCs
ATM Traffic Controller ATM AAL Library T1/E1 ATM TC Support Ethernet Library SONET Library POS Library HDLC Gigabit Ethernet/GMII datasheet ATM IMA CHI	Utopia 2 datasheet Utopia 3 datasheet SPI 3 datasheet SPI 4 Phase 1 SPI 4 Phase 2 datasheet SFI4 datasheet SFI5 datasheet SPI5 datasheet CSIX Level 1 datasheet OCh
Memory SVCs
Sparse Memory Model MT48LC16M16A2 SDRAM MT48LC16M8A2 SDRAM MT48LC8M16A2 SDRAM MT48LC4M16A1 SDRAM FLASH 256kx8	FLASH 2mx16 FLASH 2mx FLASH 4mx8 FLASH 512kx8 SDRAM 16mx16 SDRAM 2mx8
Processor SVCs
MPC603 E Transactor MPC860(T) Transactor i960 Transactor	80C186 Transactor AMBA AHB APB
General Purpose SVCs
PCI datasheet PCIX datasheet Bit Library	USB2.0 Host Controller Datasheet Reed Solomon CRC Library

PREP™ Verification Environment
Every project requires creating a new verification environment, which can take up to 12 weeks at the front-end of the product development cycle. At Zaiq, we understand that a standard, open language environment will provide you with predictable results, will shorten your product development schedule, and will allow your designers to reuse the environment, accelerating future product development cycles and saving you money. PREP is a rapidly deployable verification environment that defines standard techniques and methods for transactor development and test writing. It is an open and standards-based environment (C/C++) that uses pre-existing and third-party code.

TestBenchPlus™
TestBenchPlus is a transport layer for communicating test information between C and Verilog/VHDL. It allows concurrent communication and its API provides an easy-to-use interface for verification and behavioral models.

Click here to contact us

Back To Top

Home | About Us | Solutions | Innovation | Jobs@Zaiq |News | Partners | Site Map | Contact Us